Semiconductor Engineering

HW/SW Co-Design to Retarget the Compiler For RISC-V Custom Instructions (Tampere Univ.)

A new technical paper titled “Automatically Retargeting Hardware and Code Generation for RISC-V Custom Instructions” was ...
Semiconductor Engineering

General-Purpose 32-bit RISC-V MCU Core Expands Design Freedom

The microcontroller sector is evolving in an exciting direction by providing designers with a growing menu of choices tailored to their performance and power requirements. Unlike the classic 1990s ...
Ars Technica

A history of ARM, part 1: Building the first chip

RISC is a somewhat misleading term, as a RISC processor doesn't *have* to have fewer instructions in its ISA than a CISC system (Though RISC architectures do tend to try to do so). For example, the ...
Ars Technica

Qualcomm—one of Arm’s biggest customers—starts a RISC-V joint venture

Arm is facing down its biggest competition ever, with the up-and-coming RISC-V architecture threatening to unseat it as the CPU at the center of almost every portable device. Now, one of Arm's biggest ...