Electronics Weekly

Toshiba enables low-power SOC

Toshiba is showing a low-voltage SRAM technology at the ISSCC this week which reduces memory cell failure rate by four orders of magnitude at 0.7V, so overcoming the main challenge in achieving ...
EDN

sureCore 40nm Ultra-Low Voltage SRAM Proves World Beating Low Voltage Operation in Silicon

sureCore's newest IP delivers an impressive operating voltage range from 0.6V to 1.21V. It provides an unprecedented 20MHz cycle time at 0.6V scaling to over 300MHz at 1.21V. This performance opens ...
Design-Reuse

Renesas Technology Develops Promising Technology for Implementing On-Chip SOI SRAM of 32-Nanometer Generation and Beyond

Tokyo, June 12, 2007 −− Renesas Technology Corp. today announced the development of a technology that is effective in implementing SRAM in processes of the 32 nm (nanometer) generation and beyond, for ...
Design-Reuse

Renesas Technology Develops Technique that Overcomes Effects of Threshold Variation to Stabilize the Operation of Embedded SRAM built with 65nm Process

High yield achieved for the world's smallest level 6-transistor SRAM memory-cell area (0.494µm 2) ; stabilization technique addresses variability of transistor characteristics. Tokyo, June 15, 2006 −− ...
EDN

Renesas, Matsushita develop 45-nm on-chip SRAM stabilization technique

Renesas Technology Corp. and Matsushita Electric Industrial Co. Ltd. reported Tuesday that they have jointly developed a technique that achieves stable operation with 45-nm bulk CMOS for SRAM that can ...
Semiconductor Engineering

Scaling The Lowly SRAM

Chipmakers face a multitude of challenges at the 20nm logic node and beyond, including the task of cramming more functions on the same chip without compromising on power and performance. There is one ...