IC Compiler II, part of the Synopsys Fusion Platform, with its industry-leading capacity and throughput, accelerated implementation of the massive Colossus IPU, exceeding 59 billion transistors ...

Introduces additional technologies such as multi-objective concurrent clock and data optimization and advanced low power optimization techniques Offers early support for 10-nm process technology ...

Technology developments in latest release cement IC Compiler II's QoR leadership by delivering 5 percent better area, 5 percent better timing QoR and up to 20 percent reduction in power. With 19 of ...

ML-driven implementation in IC Compiler II and Fusion Compiler enables Samsung to achieve up to five percent higher frequency and five percent lower power Predictive ML technologies accelerate ...

Large, complex SoC designs require hierarchical layout methodologies that span multiple levels of physical hierarchy. Many EDA tools only handle two levels of physical hierarchy at a given time ...

IC Compiler II 2019 release delivers up to 2X faster throughput with next-generation distributed parallelization, intelligent scenario management, efficient infrastructure scaling, and inherent core ...

Synopsys, Inc. reaches scale for AI-driven chip designs as major semiconductor customers register the first 100 commercial tape-outs with the company's Synopsys DSO.ai (Design Space Optimization AI) ...

1.3 GHz frequency on quad-core ARM ® Cortex ™-A9 MPCore ™ processor 5X reduction in number of high power cells Correlation within 5% between synthesis and post-route timing drove predictable closure ...