Electronic Design

Transaction-Level Models Are Becoming Easier To Use

Transaction-level modeling (TLM) verification methodologies are propagating down from power users, such as large systems houses and integrated device manufacturers, to the broader design community. As ...
Electronic Design

The Rise Of Transaction-Level Modeling

After many years of expectation, we're finally seeing increased use of generally usable methods of hardware design at an abstraction level higher than RTL. This is more than just behavioral level, as ...
EDN

A new transaction standard for verification

Transaction-level modeling with SystemC has become a popular approach to verification. TLM uses function calls, rather than signals or wires, to communicate between modules. The result can be an ...
Design-Reuse

Open Core Protocol International Partnership Releases OCP SystemC Channel Version 2.1.2

PORTLAND, ORE — April 11, 2006 — Open Core Protocol International Partnership (OCP-IP) today announced the availability of the SystemC Transaction Level Monitor (TLM) Channel version 2.1.2. The ...
EDN

TLM-Driven Design and Verification using Cadence®

Transaction level modeling (TLM) is gaining favor over register-transfer level (RTL) for design components because of its many advantages—including faster design and verification times, easier ...
Semiconductor Engineering

A HIL Methodology For The SoC Development Flow

A technical paper titled “Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap” was published by researchers at University of Bremen and German Research ...